FM limiter with input level sensing and TTL level output

ABSTRACT

A system for limiting an FM signal to produce outputs which are TTL compatible, yet retain the zero crossings of the incoming FM signal as long as the amplitude of that signal remains above a chosen minimum and the frequency remains less than a chosen amount.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. patent applicationSer. No. 360,519 filed May 15, 1973, now U.S. Pat. No. 3,863,264.

BACKGROUND OF THE INVENTION

In Sequence Color and Memory Television Systems, hereinafter referred toas SECAM, the transmitted color subcarrier alternates between two colordifference signals from line to line. For this reason SECAM colordifference signals, D'_(B) and D'_(R), alternately modulate thesubcarrier. As a result of this frequency modulation, the color signalis less sensitive to differential phase and differential gain. However,since only one color difference signal is transmitted at one particulartime, some memory device must be used so that such color differencesignals are available simultaneously, say, in the receiver or imageproducing device such as a color picture tube. Herein then, lies adisadvantage of the prior art, namely non-ideal delay line.

As is well-known, the last color information to enter the SECAM delayline prior to the viewed line was the opposite color difference signal,any reflections due to such non-ideal delay line termination orconstruction will appear as cross colors at the output of the delayline. This cross color may be present from multiple reflections, withits amplitude reflecting the amount of time it has been present in thedelay line. Some direct transmission through the delay line may also bepresent, but this is principally a property of the delay lineconstruction. Such cross color represents a deterioration of atheoretical advantage over other systems of color televisiontransmission which is basic to SECAM.

A second disadvantage is that in steering the alternating lines of colorinformation from the output of the delay line and direct transmission tothe input of the D'_(R) and D'_(B) demodulators, some cross talk mustoccur in the switch. Where the signals transmitted are analog, thisrepresents a noticeable degradation of the chrominace signals.

Following the adding together of the previously mentioned colordifference signals, such signals must be amplitude limited and frequencydetected due to frequency modulation as discussed. The frequencydetector, or modulator as hereinafter referred, produces an outputdependent upon how much an input signal differs in frequency from anundiviated or rest frequency. In other words, amplitude variations ofthe color difference signals are derived in response to frequencyvariations. Thus, another disadvantage of the prior art.

As is well-known by those skilled in the art, many means of demodulationof a frequency modulated signal are known, one of which is the phaselock loop. In SECAM color systems large frequency deviations of thecolor subcarrier occur at a very fast rate. Because of this, it is verydifficult to build a phase lock loop demodulator. Inherent in theconstruction of such demodulator is high loop gain and large loopbandwidth which tend to decrease the advantage of a phase lock loopdemodulator over known methods of frequency detection.

In an article written by C. J. Byrne entitled "Properties and Design ofthe Phase Controlled Oscillator with a Sawtooth Comparator" andpublished in the Bell System Technical Journal, March 1962, meansincluding a sawtooth phase comparator are discussed to overcome thedisadvantages of the more common sinusoidal phase comparators andthereby construct a phase locked loop which would be improved in somerespects over phase locked loops mentioned above. Such improvement, ifcarried further, could be used to make a more improved phase lock loopdemodulator for a SECAM color system.

The disadvantages of the prior art were overcome by the inventiondescribed in U.S. Pat. No. 3,863,264 in that the color differencesignals are digitized at the incoming subcarrier level prior to beingapplied to the delay line. Digitizing of such signals eliminates theeffect of cross talk within the switch. Further, routing of the colordifference signals through multiple delay lines reduce reflections belowany desired level. These two advantages combine to provide virtually nocross color, a theoretical advantage of the SECAM system. A furtheradvantage is that the digitizing of the color difference signals at theincoming subcarrier level provides better equivalent noise bandwidthbecause of the digital phase detector which enables a lower bandwidthphase lock loop to be used.

The invention described in U.S. Pat. No. 3,863,264 further overcame thedisadvantage of the prior art in that any switching before or after thedelay line(s) can consist of simple logic gates. Also, by using digitalsignals corresponding to the color difference signal subcarrier anddecoding such signals based upon both a positive and a negativetransition, a very appreciable increase in decoder accuracy, speed, andequivalent noise bandwidth can be obtained.

As is well known, the trigger points of the Schmitt trigger used for thewaveform squaring circuit described in U.S. Pat. No. 3,863,264 must bechosen at a sufficiently high level to ensure enough delay between themodulator-demodulator transition and the Schmitt trigger transistion toobtain a clock pulse of usable width. To produce a usable width clockpulse for the highest level input signal which can be expected, the trippoints of the Schmitt trigger must be selected at an amplitude, say 10percent of the expected input peak value. This sets the lowest levelinput signal for which the waveform squaring circuit will produce anoutput. A disadvantage, however, is that frequently the level selectedis not low enough for reasonable fluctuations in input signal level.

BRIEF SUMMARY OF INVENTION

The present invention overcomes the disadvantage of the waveformsquaring circuit by providing an improved circuit that operates withvery high level input signals and low level input signals selectedindependently. It provides for limiting an FM signal to produce outputswhich are TTL compatible, yet retain the zero crossings of the incomingFM signal as long as the amplitude of that signal remains above a chosenminimum and the frequency remains less than a chosen amount.

It is therefore an object of the present invention to provide animproved FM limiter with input level sensing and TTL level output.

It is still another object of the present invention to provide animproved FM limiter with input level sensing and TTL level outputwhereby color difference subcarrier signals are digitized.

It is still yet another object of the present invention to provide animproved FM limiter with input level sensing and TTL level output havinga substantial dynamic range.

The subject matter of the present invention is particularly pointed outand distinctly claimed in the concluding portion of this specification.The invention, however, both as to organization and method of operationtogether with further advantages and objects thereof, may best beunderstood by reference to the following description taken in connectionwith the accompanying drawings wherein like reference characters referto like elements. It is to be understood, however, that theseembodiments are not intending to be exhausting nor limiting of theinvention but are given for purposes of illustration in order thatothers skilled in the art may fully understand the invention andprinciples thereof and the manner of applying it in particular use sothat they may modify it in various forms, each as may best be suited tothe conditions of the particular use.

IN THE DRAWINGS

FIG. 1 is a block diagram of a conventional SECAM decoder;

FIG. 2 is a block diagram of a SECAM decoder according to U.S. Pat. No.3,863,264

FIG. 3 is a schematic drawing of the waveform squaring circuit shown inFIG. 2;

FIG. 4 is a schematic drawing of the improved waveform squaring circuithaving improved dynamic range in accordance with the subject invention.

FIG. 5 is a voltage VS time graph for the waveform squaring circuit ofFIG. 3; and

FIG. 6 is a voltage VS time graph for the waveform squaring circuit ofFIG. 4.

DETAILED DESCRIPTION OF INVENTION

FIG. 1 shows a block diagram of a conventional SECAM decoder. Compositevideo, consisting of a luminance signal portion, a chrominance signalsubcarrier portion, and a synchronization signal portion, all of whichare added together in a conventional manner, is applied to a Band PassFilter and "Bell" stage 1 and a video amplifier and delay stage 2. In aconventional matter, the luminance and synchronization portions of thecomposite video signal are separated from the chrominance portion of thecomposite video signal. The luminance and synchronization signals arepassed through the video amplifier and delay stage 2 which separates thesynchronization information from the luminance, delays the luminance,then applies it to a picture tube 3. Although not shown, thesynchronization portion of the signal is used to synchronize thedeflection and timing circuits as is well-known.

The chrominance portion of the signal is then applied to a Bell havingcharacteristics opposite to the Bell of the encoder. Thus, thechrominance signal has its modulated subcarrier re-established to thecorrect amplitude. As is well-known, the chrominance portion of thecomposite video signal leaving the band pass filter and bell stage 1consists of two color difference signals corresponding to the color redminus luminance and the color blue minus luminance, hereinafter referredto as D'_(R) and D'_(B). As previously mentioned, D'_(R) and D'_(B) aretransmitted sequential i.e., a line of D'_(R), where line refers to thetime required between synchronization pulses, is transmitted followed bya line of D'_(B), etc.

The decoder is equipped with a memory 4, hereinafter referred to asDelay Line, to continuously record the color difference signaltransmitted, either D'_(R) or D'_(B), and repeating the one transmittedthe line before. Using this method, two chrominance difference signals,one restored by the delay line 4 and the other directly, are obtainedsimultaneously. An electronic double switch 5, controlled by a switchcontrol 6, is provided so that in a first position, the direct colordifference signal is applied to a first limited 7 and the memorizedcolor difference signal is applied to a second limited 8, and reversingthe direction of switching during the next line so that in a secondposition, the direct color difference signal is applied to the secondlimiter 8 and the memorized color difference signal is applied to thefirst limited 7. As can be discerned from the above, the output toeither the first limiter 7 or the second limiter 8 will be the two colordifference signals simultaneously.

Limiters 7 and 8 are used to limit any amplitude variations in eitherthe D'_(R) or D'_(B) signals occuring during the transmitting process.Following limiters 7 and 8, the color difference signals are demodulatedby demodulators 9 and 10. In principle, the demodulator supplies anoutput signal which is proportional to the deviation in theinstantaneous frequency of the D'_(R) and D'_(B) subcarrier received. Asis well-known, the demodulator which may be used is the standard phasedlocked loop to produce a signal which follows the incoming FM signalwith its voltage controlled oscillator. The phase comparator of thephase locked loop is the error detector of the loop and, as usuallyconstructed, produces an output voltage which is proportional to thesine of the phase difference of the voltage controlled oscillator, Vcoas hereinafter referred, and the incoming FM signal.

The voltages which drive the Vco corresponding to D'_(R) and D'_(B) areapplied to de-emphasis stages 11 and 12 having characteristics oppositeto the pre-emphasis of the encoder wherein the high frequency componentsare returned to their original value for reasons well-known. The outputof each de-emphasis stage is applied to matrix 13 wherein thecombination of D'_(R) and D'_(B) produce a third color difference signalE'_(g) - E'_(y) i.e., green minus luminance. The three signals, obtainedby matricing from the chrominance signals previously described, areapplied to the proper electrodes of picture tube 3. Hence, if picturetube 3 is a color picture tube, the currents of the beams caused byluminance E'_(y) are proportional to the signals red, green, and blue.

FIG. 2 is a block diagram of the SECAM decoder according to U.S. Pat.No. 3,863,264. As can be seen from this block diagram, a first waveformsquaring stage 14 and a plurality of second waveform squaring stages 15,15', 15" and 15'" have been added. In addition, first logic stage 16 andsecond logic stage 17 have been added. Replacing delay line 4 of FIG. 1is a plurality of delay lines 4', 4", 4'", and 4"". It should be notedthat at least two delay lines and second waveform squaring stages 4' -15 and 4" - 15' respectively must be used, but in no way should the ideaof more than two such sets of stages be disregarded. In addition, doubleswitch 5, limiters 7 and 8 and demodulators 9 and 10 of FIG. 1 have beenreplaced by dual demodulators 9' and 10' respectively.

Basically, the improvement comprises means to convert the frequencymodulated color difference signals D'_(R) and D'_(B) subcarrier intodigital signals. These digital signals are more easily switched andenables the use of a special phase comparator which decreases equivalentnoise bandwidth. By using digital signals it is now feasible tocompletely eliminate any cross talk due to delay lines and switching.Second waveform squaring circuits 15, 15', 15" and 15'" must be used toconvert the signal at the delay line outputs back to a digital signal.This is because the digital signal passing down the delay lines, whichin reality is a band pass filter, produces an analog signal. As thepresent invention uses digital signals, the delayed signal must bereconverted. For simplicity, all the waveform squaring circuits areidentical. Logic stages 16 and 17 are required for routing the digitalsignals into and out of the delay lines in proper sequence. Logic stages16 and 17 have circuitry therein which is determined by the number ofdelay line-waveform squaring sets used.

As only digital signals are present, such logic stages can be a simplelogic function as is well-known. The output of logic stage 17 routes thesignals to the dual demodulators. Finally, dual demodulators 9' and 10'have replaced limiters 7 and 8 and demodulators 9 and 10 respectively.By digitizing and using sawtooth phase detectors, there is no need ofseparate limiters which were required for best performance of the priorart. Demodulators 9' and 10' have the advantage over conventionaldemodulators in that its phase detector output is linear for largervalues of phase error. However, even though phase errors can be detectedvery quickly and over a large range of phase errors using the sawtoothphase comparator in the phase locked loop, described by C. J. Byrne andpreviously discussed, it is limited in that the time required todistinguish a phase error is determined by the time between the inputpositive leading edges. This is because the flip-flops, operation willbe discussed later in the specification, used have their set inputcontrolled by positive leading edges of pulses digitally derived frominput signals, originally sinusoids. In the case of SECAM, the deviationof the subcarrier is not a small percentage of the undeviated subcarrierfrequency. To adapt this type of phase comparator to use, the presentinvention uses two such flip-flops. The positive edges are used asbefore, however, the negative leading edges of the input signal and thenegative leading edges of the Vco signal are also used to drive a secondflip-flop. This doubles the gain of the phase comparators and reducestime between the input phase change and the output response of the phasecomparators so that in effect a sample is taken at each zero crossing ofan input signal rather than only the positive zero crossings. Further,the output of the phase detector flip-flops are uniquely combined toenhance the capabilities of the phase locked loop. The output of thedual demodulators are then applied to the remaining stages as discussedpreviously for the prior art.

The operation of the present invention, especially with regard todigitizing the color difference signals E'_(R) and E'_(B) subcarrier canbest be understood by referring to FIGS. 3 and 5 taken in conjunctionwith FIG. 2, As shown in FIG. 3, the waveform squaring circuit 14 takesas an input the FM signal corresponding to the color difference signalsD'_(R) or D'_(B) and produces a digital output signal. The digitaloutput signal W4, shown in FIG. 5, has been obtained from the zerocrossings of the input sinusoid.

The input FM signal, a sinusoid, is simultaneously applied to a Schmitttrigger stage 20 and the base electrode of transistor 21. As the Schmitttrigger is well-known by those skilled in the art, it will suffice toknow that waveform W₁ of FIG. 4 is produced provided the triggerpoints + V₁ and -V₁ as shown in FIG. 4 are exceeded at its input.

The emitter electrode of transistor 21 is connected to the emitterelectrode of transistor 22 and to a source of proper electricalpotential -Vee (current sources are indicated by the arrows within thesmall circles.) The base electrode of transistor 22 is connected to asource of proper electrical potential, ground. The collector electrodesof transistors 21 and 22 are directly connected to transistor pairs 23,24 and transistor pairs 25, 26 wherein each transistor pair has theiremitter electrodes connected together and to said collector electrodesof transistors 21 and 22 respectively. The base electrode of transistor24 and the base electrode of transistor 25 and the collector electrodeof transistor 23 and the collector electrode of transistor 25 areconnected together respectively, and are then connected to a source ofproper electrical potential -V_(BB) and + V_(CC) respectively. The baseelectrodes of transistors 23 and 26 are connected together and connectedto the output of said Schmitt trigger 20. The collector electrodes oftransistors 24 and 26 are connected together and to a source of properelectrical potential + V_(CC) ' via a dropping resistor 27. Also,connected directly to the collector electrodes of transistors 24 and 26is the base electrode of an inverting transistor 28 whose emitterelectrode is connected directly to a source of proper electricalpotential + V_(e) and whose collector electrode is connected to a sourceof proper electrical potential, ground, via a dropping resistor 29. Anedge triggered flip-flop 30 has its data input D also connected to theoutput of the Schmitt trigger 20 and a clock input C connected directlyto the collector electrode of transistor 28. The output waveform W4 ofthe completed circuit is taken at the logic 1 output of said flip-flop30.

To further understand circuit operation, consider the following circuitconditions exist at a time just prior to time t_(o). At such time, theinput FM signal is assumed to be crossing the zero axis in a positivedirection, hence, has reset the Schmitt trigger to produce the waveformW1 when it passed negatively through the trip point -V₁. Transistors 21,23, and 26 are reversed biased; transistors 22, 24, and 25 are forwardbiased. As a result, a current passes via transistors 22 and 25 fromthe + Vcc supply to the -Vee supply. The voltage drop across theresistor 27 will be zero so that waveform W3 is at a "high" level.Transistor 28 is reversed biased and no voltage is developed across theresistor 29. The waveform W3 is therefore at a low level. The low levelof waveform W3 being applied to the clock input of the flip-flop 30inhibits change of state of the flip-flop 30 and the waveform W4 at ahigh level is available at the 1 output of such flip-flop.

At time t_(o), transistor 21 is forward biased by the input FM signal assuch signal crosses the zero axis. As a result, current now passesthrough transistors 21 and 24 from + Vcc' through resistor 27 to -Vee.The voltage drop across the resistor 27 forward biases transistor 28.Current via resistor 29 due to the conduction of transistor 28 producesa voltage drop across such resistor which is applied to the flip-flop 30clock input. The transition from the "low" level to the high level ofwaveform W3 transfers the level of waveform w1 to the output, hencewaveform W4 is low.

At a next time T1, the Schmitt trigger 20 is tripped by the input FMsignal reaching a second trip voltage + V₁. Transistors 23 and 26 becomeforward biased; transistors 24 and 25 are reversed biased. As transistor22 is now reversed biased, no current is passed through the resistor 27.As a result, transistor 28 is reversed biased to produce the waveformW3. Output waveform W4 therefore remains at the low level. At a nexttime T2, it becomes obvious that the waveform W4 goes to a high level.As can be discerned from the above discussion, the output waveform W4changes from the high to low state or vice-versa at each zero crossingof the input FM signal. The zero crossings are thus preserved as isrequired for proper operation of the dual demodulator which will becovered in detail later in the specification.

It should be noted that transistors 21, 22, 23, 24, and 25 are connectedin a manner well-known as a modulator-demodulator circuit and may be ofdiscrete components or an integrated circuit, as shown by the dashedlines, such as a Motorola, Inc. MC 14966 Modulator-Demodulator. Further,the waveform squaring circuits 15, 15', 15" and 15'" following the delaylines are identical to that shown in FIG. 3 and is incorporated forreasons already discussed.

As is well-known, the trigger points +V₁ and -V₁ of the Schmitt triggermust be chosen at a sufficiently high level to insure enough delaybetween the modulator-demodulator transition and the Schmitt triggertransistion to obtain a clock pulse of usuable width. To produce ausuable width clock pulse for the highest level input signal which canbe expected, the trip points ± V₁ of the Schmitt trigger must beselected at an amplitude, say 10 percent of the expected input peakvalue. This sets the lowest level input signal for which the waveformsquaring circuit will produce an output. The level selected frequentlyis not low enough for reasonable fluctuations in input signal level. Theembodiment in FIG. 4 overcomes this limitation by allowing selection ofthe Schmitt trigger levels ± V₁ for the lowest level input andestablishing the clock pulse width for the highest level input by afixed delay.

The operation of the FIG. 4 embodiment, especially with regard todigitizing the color difference signals D'_(R) and D'_(B) subcarrier canbest be understood by referring to FIG. 6 in conjunction with FIG. 4. Asshown, the waveform squaring circuit 14' takes as an input the FM signalcorresponding to the color difference signals D'_(R) and D'_(B) andproduces a digital output signal. The digital output signal W9, shown inFIG. 6, has been obtained from the zero crossings of the input sinusoid.

The input FM signal, a sinusoid, is simultaneously applied to a Schmitttrigger stage 20' and the input to a comparator stage 250. Again, as theSchmitt trigger is well-known by those skilled in the art, it willsurfice to know that the waveform W5 of FIG. 6 is produced provided thetrigger points ± V₁ ' as shown are exceeded at its input. The output ofthe Schmitt trigger, waveform W5, is applied to the data input D of anedge triggered flip-flop 30' via a plurality of series connected delaymeans 225 and 226, such for example, as a conventional "exclusive ORgate". Such logic is well-known and will not be described in detail. Thedata input to edge triggered flip-flop 30' is therefore the waveform W6,delayed by T, hereinafter referred to as tau, dependent upon the numberof delay means used. In the embodiment of FIG. 4 the delay between thewaveforms W5 and W6 defines 2 times tau. Similarly, the output of thecomparator 250 is the waveform W7 including comparator delay T₂ and isused to generate the waveform W8 applied to clock input C of edgetriggered flip-flop 30' via the gate 227, also shown as an exclusive ORgate. Gate 227 is also driven by the waveform W6.

The comparator 250 (comparator 250 can be a conventional comparator suchas the Signetics NE529) retains the zero crossing of the input signalbecause of its extremely high gain and the Schmitt trigger determines ifthe input signal is of sufficient amplitude to be a valid input. Thus,if the input signal is above the amplitude of the upper and lower trippoints of the Schmitt trigger 20', the Schmitt trigger output willfollow the zero crossings of the incoming signal but will have itstransitions delayed an amount which depends upon the input signalamplitude. For very high amplitude inputs, the Schmitt triggertransitions will occur practically simultaneously with the comparatortransitions with an ensured minimum time delay between the outputtransitions of the Schmitt trigger and the output of the comparator asshown in FIG. 6 due to the delay means.

Because the clock pulse width to edge triggered flip-flop 30' aredetermined by the difference in time between the input signal zerocrossings and the Schmitt trigger transition, a minimum pulse widthindependent of input signal amplitude sufficient to clock the data inputD of the edge triggered flip-flop 30' is assured. The leading edge ofthe waveform W8, generated by exclusively oring the waveforms W6 and W7,transfers the data to the output of the waveform squaring circuit and asdiscerned from waveform W9, follows the input signal zero crossings withslight delay which is caused by the delay of the comparator 250. If,however, the input signal falls below the level of the upper or lowertrip points of the Schmitt trigger, the data input to the edge triggeredflip-flop 30' will not change. This then provides a clear indication asto whether the FM subcarrier is not present, or is too low a level.

The improved circuit will therefore operate with very high level inputsignals and low level input signals selected independently which is theessence of the improvement over the previous embodiment. It should bepointed out however, that the amount of delay which is added directlylimits the frequency range over which the circuit retains the fulldynamic range which is selected. As an example, the maximum clock pulsewidth of the embodiment using two delay means would be

    W = π/2 radians + 2 T.sub.1 - T.sub.2

at the lowest frequency and level which would produce an output. Thisimposes the limitation that

    2 T.sub.1 - T.sub.2 < π/2 radians

at the highest frequency and level which will produce an output. Thus,with two exclusive OR gate delay means and the comparator having typicaldelay times of 15 ns and 10ns respectively, the maximum input frequencywould be approximately equal to 12 MHz as mathematically found by

    2 (15ns) - 10ns ≦1/4f

or

    f ≦ (1/80 ms) ≈ 12 MHz.

The invention is claimed in accordance with the following:
 1. An analoglimiter with input level sensing and TTL level output,comprising:Schmitt trigger means responsive to the amplitude of ananalog signal applied thereto for providing a first square wave;comparator means responsive to the zero crossings of an analog signalapplied thereto for providing a second square wave; means responsive tosaid first and second square waves for providing a data signal and atiming signal; and means responsive to both said data and timing signalsfor providing an output square wave having the zero crossings of saidanalog signal.
 2. The method of deriving a digital output signal inresponse to an analog input signal where the output signal maintains thezero crossings of the analog input comprising the steps of:applying theanalog input signal to a means responsive to the amplitude of the analoginput signal; applying the analog input signal to a means responsive tothe zero crossings of the analog input signal; generating a first outputsquare wave defining a data signal in response to the amplitude of theanalog input signal; generating a second output square wave in responseto the zero crossings of the analog input signal; applying said firstand second output square waves to a means responsive to both said firstand second output square waves; generating a clock signal in response tothe anticoincidence of both said first and second output square waves;applying both said data and clock signals to a means responsive to saiddata signal and said clock signal; and generating the digital outputsignal in response to said data signal and said clock signal.